1. Field of the Invention
The present invention relates to a level shifter circuit having a screening test function which efficiently destroys latent manufacturing defects which lead to initial failures after shipping, such as in a gradation selection circuit which selects and outputs one of plural analog gradation voltages, to a drive circuit in which the level shifter circuit is installed, to a display in which the drive circuit is installed, and to a stress test method for the gradation selection circuit.
2. Description of the Related Art
A high voltage stress test is a general method for screening the initial failure of a display drive LSI. This high voltage stress test is a test method which, in the stress test before shipping, applies a voltage higher than the LSI drive voltage applied to the LSI in use, and thus reveals latent element defects in the LSI more effectively (i.e., latently defective parts are destroyed prior to shipping). The high voltage stress test time is determined by taking account of a voltage acceleration component (i.e., how much the revealing of an element defect is accelerated by applying a voltage), and a temperature acceleration component (how much the revealing of an element defect is accelerated by temperature), estimating the initial market failure rate, and setting a target failure rate according to the application of the LSI and the specification required of the LSI so that the initial failure rate is less than the target failure rate.
In recent microfabrication wafer processes, high voltage-resisting elements which can apply a high voltage such as 16 V have become indispensable, and it is important to screen for latent defects which could lead to the initial failure of these elements by a high voltage stress test. In order to maximize the test coverage of such screening, a full gradation scan test of the gradation selection circuit used for the display drive (generally, a digital analog converter (DAC)) must be performed.
FIG. 17A shows the construction of prior-art level shifter circuits 604 and 605 and gradation selection circuit 601, and FIG. 17B shows the operating state of the level shifter circuits 604 and 605 during a prior-art stress test.
The gradation selection operation of the gradation selection circuit 601 will first be described using FIG. 17A. The level shifter circuit 604 applies a control signal BIT0b from an output terminal OUTb to the gates NOb1 and NOb3 of an NMOS transistor N0b1 of the gradation selection circuit 601. The level shifter circuit 604 also applies a control signal BIT0 from the output terminal OUT to the gates of the NMOS transistors N02 and N04 of the gradation selection circuit 601. The control signal BIT0b is a signal which is the logical reverse of the control signal BIT0, therefore, one of the control signals BIT0 and BIT0b is H (high) level, and the other is L (low) level. The level shifter circuit 605 applies a control signal BIT1b from the output terminal OUTb to the gate of the NMOS transistor N1b12 of the gradation selection circuit 601. The level shifter circuit 605 applies a control signal BIT1 from the output terminal OUT to the gate of the NMOS transistor N134 of the gradation selection circuit 601. The control signal BIT1b is a signal which is the logical reverse of the control signal BIT1, therefore, one of the control signals BIT1 and BIT1b is H level, and the other is L level. By controlling the gradation selection circuit 601 by the level shifter circuits 604 and 605, one of the analog gradation voltages V1–V4 is output from the gradation selection circuit 601.
FIG. 18A shows the construction of the prior-art level shifter circuit 700 (the level shifter circuit 604 or 605 in FIG. 17A), and FIG. 18B shows the operating state of the level shifter circuit 700 during a prior-art stress test.
As shown in FIG. 18A, the level shifter circuit 700 has a first reference potential supply line 701 to which an L level (GND) potential (or voltage) is applied, a second reference potential supply line 702 to which an H level potential (or voltage) is applied, a first PMOS transistor 711 and first NMOS transistor 712 connected in series sequentially from the second reference potential supply line 702 side, a second PMOS transistor 721 and second NMOS transistor 722 connected in series sequentially from the second reference potential supply line 702 side, a first connection line 714 which connects a gate 715 of the first PMOS transistor 711 to a drain 723 of the second NMOS transistor 722, and a second connection line 724 which connects a gate 725 of the second PMOS transistor 721 to a drain 713 of the first NMOS transistor 712. As shown in FIG. 18A, the level shifter circuit 700 further has a first input line 731 connected to the gate of the first NMOS transistor 712 into which a first input signal IN is input, a second input line 732 connected to the gate of the second NMOS transistor 722 into which a second input signal INb (i.e., a signal which is the logical reverse of the first signal IN) is input, a first output line 741 connected to the drain 713 of the first NMOS transistor 712 which outputs a first output signal (i.e., a control signal which controls the gradation selection circuit) BITnb (n=0, 1, . . . ), and a second output line 742 connected to the drain 723 of the second NMOS transistor 722 which outputs a second output signal (i.e., a control signal which controls the gradation selection circuit) BITn (n=0, 1, . . . ). The prior-art level shifter circuit is disclosed, for example, by Japanese Patent Kokai (Laid-Open) Publication No. 2002-84184.
Next, the stress test method of the gradation selection circuit (four gradations (2-BIT gradation) DAC) 601 of FIG. 17A will be described. To apply the test voltage to all six NMOS transistors shown in FIG. 17A, N0b1, N02, N0b3, N04, N134 and N1b12, it is necessary to perform a high voltage stress test with all four patterns of the four gradations of the analog output voltages V1–V4. This is because, to destroy the latently defective parts in the NMOS transistors N02 and N04 and the NMOS transistors N0b1 and N0b3 which are controlled by the control signal BIT0 or BIT0b, these four NMOS transistors must be switched ON, and to destroy the latently defective parts in the NMOS transistors N134 and N1b12 which are controlled by the control signal BIT1 or BIT1b, these two NMOS transistors must be switched ON. For example, in an n-BIT gradation DAC, the number of transistors is (21+22+23+ . . . +2n). Therefore, in an 8-BIT gradation DAC, the number of transistors per output is 510, and in an 8-BIT gradation 642 output DAC, the number of transistors is 510×642=327,420. Also, in order to apply a high voltage stress to the (21+22+23+ . . . +2n) transistors, 2n patterns must be tested.
However, in flat panel displays which display digital images or television, etc., in recent years, higher gradation displays, finer displays and display drive LSI with multiple outputs (increase in drive outputs) have come into demand. For example, the source electrode drive LSI for TFT liquid crystal panels have shifted from a 6-BIT gradation (about 260,000 colors) to an 8-BIT gradation (about 16,780,000 colors), moreover, trials are now being performed on a 10-BIT gradation (about 1 billion colors), and even higher gradations are expected to be realized in future. As regards the number of drive outputs of display drive LSI, in addition to the usual 384 outputs, 480 outputs, 642 outputs and even more outputs have come into practical use. To increase display contrast, there is a trend to increase the display drive voltage and LSI power supply voltage. Moreover, to provide the multiple gradations and multiple outputs of display drive LSI, there is a need for display drive LSI with very large-scale integrated circuits, and in costly display devices such as large televisions it is a matter of particular importance to reduce the initial failure rate.
However, in a prior-art level shifter circuit which controls the transistor of a DAC forming a gradation selection circuit, as shown in FIG. 18B, there are only two combinations of the output signals OUT (BIT0, BIT1) and OUTb (BIT0b, BIT1b) with the input signals IN and INb (output signal OUT is H level and OUTb is L level, or output signal OUT is L level and OUTb is H level), so a very large number of stress test patterns had to be input, and the stress test time was very long.